The demands for smaller, higher performance semiconductor devices, which support portable electronic devices, have motivated the development of new techniques for producing smaller and less expensive semiconductor devices. Modern consumer electronics particularly personal portable devices, such as cellular phones, digital cameras, and music players, require increasing integrated circuit die content to fit an ever-shrinking physical space as well as increasing performance. One of these technologies involves packaging the integrated circuit die in as small a form factor as possible and manufacturing the integrated circuit die as efficiently as possible.
Semiconductor packaging technology is one of the key technologies for realizing small, highly performing electronic devices. A variety of types of semiconductor packages have evolved over time in order to realize ever increasing high density packaging, such as the dual inline package (DIP), the small outline package (SOP) and the ball grid array (BGA). A key issue with implementing high density and performing electronics is that the area occupied by a semiconductor chip's package should be reduced when possible, which is often accomplished by reducing the width of the package's wires, the pitch of the package's external terminals and the size of the package's outer casing.
First-level IC packaging performs the function of electrically connecting a silicon chip to a carrier enabling it to be safely handled and assembled into an electronic system. Key objectives of IC packaging are to route the connections of the chip to a carrier substrate in a cost-effective way, to minimize the form factor of the final IC package, and to minimize degradation of electrical performance that can be caused by packaging parasitics such as inductance, resistance, and capacitance. Therefore, an electrical objective is to maintain signal integrity despite the presence of packaging parasitics. In other words, the electrical objective is to provide an electrical path in the package on which electrical data can travel without undue noise, distortion, or interference from parasitic elements along that path.
The negative effects of these parasitics can increase with operating frequency. As chip and system speeds now routinely operate at significantly higher frequencies, it is more necessary than ever to carefully select packaging technologies, which do not interfere with the proper functioning of the system. Currently, the two of the major packaging technologies used within the IC packaging industry for chip-to-carrier, or “first-level”, interconnections: are Wire-based interconnection (90-95% of chips connected) and bump-based interconnection (5-10% of chips connected).
In the case of the wire-based interconnection, a wire is bonded from a bond pad on the silicon chip to a bond finger on a carrier substrate. The resulting interconnection is referred to as a wirebond and the package is referred as a wire-based IC package. Electrical parasitics from this method of interconnection arise primary from the loop inductance of wire, the self inductance of the wire, capacitive coupling. With this method, functional limitations may arise with increased frequencies. The practical limit for this method is in large part determined by the frequency.
With bump-based interconnects, solder bumps are used instead of bonding wires. These bumps are located on the chip and each bump is soldered to a corresponding pad on a carrier substrate. During package assembly, this array of bumps on the chip must be carefully aligned with an associated array of pads on the carrier substrate. The interconnection scheme from chip bump to carrier pad needs to be determined at the time that the carrier substrate is designed; it can be difficult and expensive to reassign a bump on the chip to a different pad on the carrier substrate from the one placed directly below it. High density bump-based packages typically drive a much higher chip carrier, or substrate cost to route the bumps.
In contrast, the wire-based interconnect method allows the connection scheme between the bond pads and bond fingers to be determined at the later IC packaging manufacturing phase. This allows for electrical design flexibility at a later stage of IC packaging, which is generally desirable.
Thus, a need still remains for an integrated circuit package system to improve integrated circuit packages particularly processing, handling, and transporting mold segments. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.